Each FF has J and K inputs at the 1 level,so that it will
change states (toggle) whenever the signal on CLK input goes from HIGH to LOW.
The Clock pulses are applied only to the CLK input of FF Q0.Output Q0 is connected
to the CLK input of FF Q1, and output Q1 is connected to the CLK input of FF Q2.
The Following important points should be noted :
1. Flip-flop Q0 toggles on the negative-going transition of each input clock pulse.
Thus,the Q0 output waveform has a frequency that is exactly one-half of the clock pulse frequency.
2. Flip-flop Q1 toggles each time the Q0 output goes from HIGH to LOW. The Q1 waveform has a frequency equal
to exactly one-half the frequency of the Q0 output and therefore one-fourt of the clock frequency.
3. Flip-flop Q2 toggles each time the Q1 output goes from HIGH to LOW. Thus, the Q2 waveform has one-half the frequency
of Q1 and therefore one-eighth of the clock frequency.
4.Each FF output is a square wave ( 50 Percent duty cycle).
As described above each FF divides the frequency of its inpt by 2. THus, if we were to add a fourth
FF to the chain, it would have a frequency equal to one-sixteenth
of the clock frequency, and so on. Using the appropraite number of FF, this circuit
could divide a frequency by any power of 2. Specially, Using N flip-flops would produce an output frequency
from the last FF which is equal to 1/2 N of the input frequency.
This Application of flip-flops is reffered to as frequency division.For example,your wristwatch is no doubt
a "quartz" watch. the term quart watch means that a quartz crystal is used to generate a very stable oscillator frequency.
The natural resonant frequency of the quartz crystal in your watch is likely 1 MHz or more. In order to advance
the "seconds" display once every second, the oscillator frequency is divided by a value that will produce a very
stable and accurate 1 Hz output frequency.
COUNTING OPERATION
In addition to functioning as a frequency divider also operates a binary counter.This can be demonstrated by examining
the squence of states of the FFs after the occurrence of each clock pulse.
Binary Counters
Then we can see that a counter is nothing more than a specialised register or pattern generator that produces a specified output pattern or sequence of binary values (or states) upon the application of an input pulse signal called the “Clock”.The clock is actually used for data transfer in these applications. Typically, counters are logic circuits that can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal.
Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or “cascaded” together to form a “divide-by-n” binary counter where “n” is the number of counter stages used and which is called the Modulus. The modulus or simply “MOD” of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one complete cycle.
Then a counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2n-1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on.
An example of this is given as.
- 3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)
- 4-bit Binary Counter = 24 = 16 (modulo-16 or MOD-16)
- 8-bit Binary Counter = 28 = 256 (modulo-256 or MOD-256)
- and so on..